System-on-a-Chip (SoC) designs integrate many or all components of a computer or other electronic device or system into an integrated circuit chip, and are commonly used to consolidate components for increased system performance and ease of manufacturing. A typical SoC includes one or more microcontrollers (e.g., microprocessor or DSP core), memory, peripherals, interfaces, timing sources, voltage regulators and power management circuits, and external interfaces.
The components of an SoC are connected by either a proprietary or industry-standard on-chip bus, which allows the components of the SoC to interface with each other. One such industry standard bus is the Advanced Microcontroller Bus Architecture (AMBA™) from ARM Ltd., a common 32-bit architecture for embedded CPUs. The AMBA on-chip bus is an open specification that serves as a framework for SoC designs. Use of the AMBA specification can bind library cores together and is an enabler of library component reuse. By designing to the standard AMBA interface, modules can be implemented and tested without prior knowledge of the system into which the component will finally be integrated.
The AMBA bus includes two different protocols, Advanced High performance Bus (AHB) and Advanced Peripheral Bus (APB). The AHB bus is higher speed than the APB bus and typically acts as the high-performance system backbone bus.
FIG. 1 is block diagram of a typical AMBA system 10 and shows the integration of the AMBA AHB and APB buses using a multi-layer interconnection matrix. The multiple layers include an AHB matrix 12 which connects AHB-Lite masters 14 to AHB-Lite slaves 16, as well as an AHB/APB bridge 18 that connects APB slaves 20 to the AHB matrix 12. A bus master is able to initiate read and write operations by providing an address and control information. Typically, only one master is allowed to actively use the bus at any one time. A bus slave responds to a read or write operation within a given address-space range. The slave signals back to the active master the success, failure or waiting of the transfer.
The masters and slaves used in the system 10 can be standard AMBA AHB components, or “AHB-Lite” components (as shown in FIG. 1). AHB-Lite is a subset of the full AHB specification and can be used in designs where a single bus master is used, either a simple single-master system, or a multi-layer AHB system where there is only one AHB master per layer. AHB-Lite simplifies the AHB specification by removing the protocol required for multiple bus masters, so that masters designed to the AHB-Lite interface specification can be simpler in terms of interface design, as compared to a full AHB master.
FIG. 2 is a block diagram illustrating an AMBA bus system 40 including two integrated circuit chips. A common approach is to split the components of a SoC over two or more chips, such as chips 42 and 44, which communicate with each other using a standard interface such as AMBA. Typically, the AHB and APB bus interface is made available outside of each chip for each master and slave, to allow the interfacing to other chips. In FIG. 2, the AHB buses 46 and APB buses 48 interconnect the two chips 42 and 44, where chip 44 provides 12 extra masters and slaves for the system 40.
A disadvantage of the system as shown in FIG. 2 is that the complexity and the overall cost of the system grows exponentially based on the number of AHB and APB interface buses needed across all chips in the entire system. On average, the number of lines needed for each AHB and APB bus is in the order of 100 or above; this number depends on the number of addresses needed by the slaves. This approach becomes impractical to achieve when the number of AHB and APB interface buses needed reaches the limit of I/O pins available. In other words, the maximum number of AHB and APB interface buses depends directly on the number of I/O pins available.
Thus, for example, in the example of FIG. 2, if the average number of lines per bus is 100, and this number of lines is multiplied by the number of masters and slaves (12), then at least 1,200 I/O pins are needed to satisfy the interface requirements. Thus if multiple masters and slaves are included in the system, as is commonly the case, the number of communication lines needed can increase greatly, which can be impractical and/or greatly increases the complexity and expense of the SoC due to the high demand of I/O pins.
Accordingly, a method and system of connecting components of a system on a chip with a bus architecture without requiring the numerous communication lines and accompanying complexity, would be desirable in many applications.